Memory Consistency and Process Coordination for SPARC Multiprocessors

Simple and unified non-operational specifications of the three memory consistency models Total Store Ordering (TSO), Partial Store Ordering (PSO), and Relaxed Memory Order (RMO) of SPARC multiprocessors are presented and proved correct. The specifications are intuitive partial order constraints on possible computations and are derived from natural successive weakening of Lamport’s Sequential Consistency. The formalisms are then used to determine the capabilities of each model to support solutions to critical section coordination and both set and queue variants of producer/consumer coordination without resorting to expensive synchronization primitives. Our results show that none of RMO, PSO nor TSO is capable of supporting a read/write solution to the critical section problem, but each can support such a solution to some variants of the producer/consumer problem. These results contrast with the two previous attempts to specify these machines, one of which would incorrectly imply a read/write solution to the critical section problem for TSO, and the other of which is too complicated to be useful to programmers. Our general framework for defining and proving the correctness of the memory consistency models was key in uncovering the previous error and in achieving our simplification, and hence may be of independent interest.